A Ping-Pong Integrating FFE for Wireline SerDes Applications

Abstract

This paper presents a ping-pong current-integrating feed-forward equalizer (PPI-FFE) architecture for high-speed wireline receivers, enabling the realization of multi-tap analog FFE with reduced hardware complexity. By leveraging time-interleaved integration and ping-pong operation, the proposed architecture decouples the number of FFE taps from the number of first-rank track-and-hold (T/H), significantly reducing the required number of jitter- and skew-sensitive sampling elements and unit Gm-cells compared to conventional interleaved discrete-time FFE implementations. As a result, the architecture offers a more compact and routing-friendly solution, mitigating parasitic and matching challenges in analog FFE design. As a proof of concept, a reconfigurable 4-tap PPI-FFE is implemented in 22-nm FDSOI technology targeting a 112-Gb/s PAM-4 receiver. Post-layout simulation results demonstrate effective ISI mitigation over a 32-dB-loss channel at Nyquist, with 26 mW power consumption for the core FFE and clock generation circuitry. Comparison with recent mixed-mode receivers shows superior area and power efficiency for the core FFE functionality.