Correction to “Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression”

IF 1.8 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems Pub Date : 2026-06-04 DOI:10.1049/cds2/9810389

引用次数: 0

Abstract

A. Ghaemnia, J. Yang, X. Fei, and G. Zhang, Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression, IET Circuits, Devices & Systems, 2026, 9011136, 15 pages, 2026 https://doi.org/10.1049/cds2/9011136.

In the Funding section, the text “No funding was received for this manuscript.” was incorrect.

The correct funding statement is displayed below:

This work was supported by the Key R&D Program of “Science, Technology and Innovation Yongjiang 2035” (Priority Emergency Project) under Grant No. 20251ZDYF020574.

We apologize for this error.

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“用带周跳抑制的双棱低占空比PFD快速锁定跳频锁相环”的修正

A. Ghaemnia, Yang J., Fei X., Zhang G.，基于双边缘低占空比PFD的快速锁定跳频锁相环，IET电路，2026,9011136,15页，2026 https://doi.org/10.1049/cds2/9011136.In资金部分，“未收到此手稿的资金”的文本是错误的。本研究由“永江2035科技创新”重点研发计划（重点应急项目）资助，批准号：20251ZDYF020574。我们为这个错误道歉。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Iet Circuits Devices & Systems 工程技术-工程：电子与电气

CiteScore

3.80

自引率

7.70%

发文量

审稿时长

3 months

期刊介绍： IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers