Memory-power efficient 2-D FIR filter designs exploiting rotational and octagonal symmetry using parallel DA for image processing

Venkata Krishna Odugu , Swathi Odugu , Harish Babu Gade , Banothu Bapuji
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Abstract

This paper presents efficient VLSI architectures for 2-D FIR filters exploiting Four-Fold Rotational Symmetry (FRS) and Octagonal Symmetry (OS) in the coefficient matrices, combined with parallel processing and a dual-port Distributed Arithmetic (DA)–based computation approach. By incorporating symmetry properties, the number of unique filter coefficients is significantly reduced, resulting in substantial savings in multipliers and overall arithmetic complexity. The remaining multiplications are implemented using a modified dual-port LUT-based DA, which minimizes memory size, power consumption, and critical path delay compared to conventional DA techniques. Parallel processing with a block size L is employed to enhance throughput by a factor of L, while maintaining efficient memory usage. Two symmetry-specific filter architectures, one based on four-fold rotational symmetry and the other on octagonal symmetry, are designed, analyzed, and optimized using the proposed DA scheme. Each architecture is implemented in Verilog HDL and synthesized on an FPGA using Xilinx tools to obtain hardware utilization, timing, and power metrics. Further, ASIC synthesis using Cadence Genus in 45-nm CMOS technology is performed to evaluate area, delay, and power, followed by physical design and layout generation using Innovus. The ASIC synthesis results for the proposed architectures in 45 nm CMOS technology show that the OS architecture achieves a maximum reduction of 97.42% in Area Delay Product (ADP) and 89.41% in Power Delay Product (PDP)compared to the state-of-the-art designs. Moreover, the FRS architecture achieves a balanced optimization in ADP reduction by 89.15% and a reduction in PDP by 29.43%. Statistical validation for images proves that these huge hardware reductions are achieved while maintaining a quality retention rate of 98% in SSIM and PSNR values of 0.932 and 29.52 dB, respectively, demonstrating their high utility for real-time vision and image dehazing applications.
利用旋转和八角形对称的二维FIR滤波器设计,利用并行DA进行图像处理
本文提出了利用系数矩阵中的四重旋转对称(FRS)和八边形对称(OS)的二维FIR滤波器的高效VLSI架构,并结合并行处理和基于双端口分布式算法(DA)的计算方法。通过结合对称特性,可以显著减少唯一滤波器系数的数量,从而大大节省乘法器和整体算术复杂度。其余的乘法使用改进的双端口基于lut的数据处理实现,与传统的数据处理技术相比,它最大限度地减少了内存大小、功耗和关键路径延迟。采用块大小为L的并行处理将吞吐量提高1倍,同时保持有效的内存使用。设计、分析和优化了基于四重旋转对称和基于八角形对称的两种对称滤波器结构。每个架构都在Verilog HDL中实现,并使用Xilinx工具在FPGA上合成,以获得硬件利用率,时序和功耗指标。此外,在45纳米CMOS技术中使用Cadence Genus进行ASIC合成,以评估面积,延迟和功耗,然后使用Innovus进行物理设计和布局生成。基于45 nm CMOS技术的ASIC综合结果表明,与最先进的设计相比,该OS架构的面积延迟产品(ADP)和功率延迟产品(PDP)分别降低了97.42%和89.41%。此外,FRS架构实现了ADP降低89.15%和PDP降低29.43%的平衡优化。对图像的统计验证证明,在SSIM和PSNR分别为0.932和29.52 dB的情况下,在保持98%的质量保持率的同时,实现了这些巨大的硬件减少,表明了它们在实时视觉和图像去雾应用中的高实用性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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