A Fast Convergence Background Calibration Technique for Gain Nonlinearity in Pipeline ADCs

Abstract

A novel background calibration technique for gain nonlinearity in pipeline analog-to-digital converters (ADCs) with fast convergence is presented in this brief. The proposed method leverages dual-comparator parallel calibration (DCPC) and multiplying digital-to-analog converter (MDAC) dither injection to extract inter-stage gain error (IGE), gain nonlinearity, and capacitor mismatch. This method employs a large dither window and a low-complexity algorithm to achieve fast convergence. Compared with prior dither-based calibration works, this work avoids introducing additional residue signal swing increment, thereby relaxing the design requirements of the residue amplifier (RA). Simulations demonstrate that the calibration technique improves the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 30.5 and 36.6 dB, respectively, in a 14-bit 1-Gsps pipeline ADC affected by IGE, gain nonlinearity, capacitor mismatch, and −74 dB thermal noise. The convergence requires only $1.25{\,}\times{\,}10^{6}$ conversions, representing an at least eightfold improvement over prior art.