{"title":"Nighthawk: Zero-Copy Cache Quarantine for Invisible Speculation","authors":"Minwoo Jang;Sungju Kim;Daehoon Kim","doi":"10.1109/LCA.2026.3677441","DOIUrl":null,"url":null,"abstract":"Out-of-order execution enhances processor performance but introduces transient execution vulnerabilities that leak confidential data via microarchitectural side effects. Existing defenses often necessitate invasive hardware modifications—such as dedicated buffers or complex forwarding logic—resulting in prohibitive performance degradation. We propose <monospace>Nighthawk</monospace>, a lightweight defense that repurposes existing cache ways to isolate speculative loads without the area overhead of auxiliary structures. <monospace>Nighthawk</monospace> introduces an in-cache quarantine mechanism that dynamically allocates a specific cache way to buffer speculative data, effectively eliminating the data-copy latency inherent in decoupled buffer designs. By integrating this mechanism with Speculative Taint Tracking (STT), we transform STT’s restrictive stall policy into a prefetch-but-quarantine strategy. This approach recovers memory-level parallelism by allowing speculative misses to proceed into the quarantined way while blocking microarchitectural propagation until resolution. Evaluation using gem5 on SPEC CPU2006/2017 benchmarks demonstrates that <monospace>Nighthawk</monospace> reclaims performance lost to STT, reducing execution time by 6.2% on average and up to 28.8% for memory-intensive workloads, offering a more practical design point for secure high-performance processors.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"134-137"},"PeriodicalIF":2.0000,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11456048/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/25 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Out-of-order execution enhances processor performance but introduces transient execution vulnerabilities that leak confidential data via microarchitectural side effects. Existing defenses often necessitate invasive hardware modifications—such as dedicated buffers or complex forwarding logic—resulting in prohibitive performance degradation. We propose Nighthawk, a lightweight defense that repurposes existing cache ways to isolate speculative loads without the area overhead of auxiliary structures. Nighthawk introduces an in-cache quarantine mechanism that dynamically allocates a specific cache way to buffer speculative data, effectively eliminating the data-copy latency inherent in decoupled buffer designs. By integrating this mechanism with Speculative Taint Tracking (STT), we transform STT’s restrictive stall policy into a prefetch-but-quarantine strategy. This approach recovers memory-level parallelism by allowing speculative misses to proceed into the quarantined way while blocking microarchitectural propagation until resolution. Evaluation using gem5 on SPEC CPU2006/2017 benchmarks demonstrates that Nighthawk reclaims performance lost to STT, reducing execution time by 6.2% on average and up to 28.8% for memory-intensive workloads, offering a more practical design point for secure high-performance processors.
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.