Nighthawk: Zero-Copy Cache Quarantine for Invisible Speculation

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-25 DOI:10.1109/LCA.2026.3677441
Minwoo Jang;Sungju Kim;Daehoon Kim
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引用次数: 0

Abstract

Out-of-order execution enhances processor performance but introduces transient execution vulnerabilities that leak confidential data via microarchitectural side effects. Existing defenses often necessitate invasive hardware modifications—such as dedicated buffers or complex forwarding logic—resulting in prohibitive performance degradation. We propose Nighthawk, a lightweight defense that repurposes existing cache ways to isolate speculative loads without the area overhead of auxiliary structures. Nighthawk introduces an in-cache quarantine mechanism that dynamically allocates a specific cache way to buffer speculative data, effectively eliminating the data-copy latency inherent in decoupled buffer designs. By integrating this mechanism with Speculative Taint Tracking (STT), we transform STT’s restrictive stall policy into a prefetch-but-quarantine strategy. This approach recovers memory-level parallelism by allowing speculative misses to proceed into the quarantined way while blocking microarchitectural propagation until resolution. Evaluation using gem5 on SPEC CPU2006/2017 benchmarks demonstrates that Nighthawk reclaims performance lost to STT, reducing execution time by 6.2% on average and up to 28.8% for memory-intensive workloads, offering a more practical design point for secure high-performance processors.
夜鹰:用于不可见推测的零副本缓存隔离
乱序执行提高了处理器性能,但引入了临时执行漏洞,通过微体系结构副作用泄露机密数据。现有的防御通常需要侵入性的硬件修改——比如专用缓冲区或复杂的转发逻辑——从而导致令人生畏的性能下降。我们提出了夜鹰,一个轻量级的防御,重新利用现有的缓存方式来隔离推测负载,而不需要辅助结构的区域开销。Nighthawk引入了一种缓存内隔离机制,该机制动态地分配特定的缓存方式来缓冲推测数据,有效地消除了解耦缓冲区设计中固有的数据复制延迟。通过将该机制与推测性污点跟踪(STT)集成,我们将STT的限制性失速策略转换为预取但隔离策略。此方法允许推测错误以隔离的方式进行,同时阻止微架构传播,直到解决为止,从而恢复内存级并行性。在SPEC CPU2006/2017基准测试中使用gem5进行的评估表明,Nighthawk回收了STT的性能损失,平均减少了6.2%的执行时间,对于内存密集型工作负载减少了28.8%,为安全的高性能处理器提供了更实用的设计点。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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