Statistical Performance Analysis Framework for Bundled-Data Asynchronous Circuits With Dynamic Voltage Scaling

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2026-03-28 DOI:10.1049/cdt2/1529127

Maryem Benyoussef, Claude Thibeault, Yvon Savaria

引用次数: 0

Abstract

As the demand for low-power electronic products grows, asynchronous circuits are considered a good alternative for addressing power consumption issues. Applying dynamic voltage scaling (DVS) in asynchronous circuits can further improve their power efficiency. However, asynchronous circuits face challenges, such as performance analysis considering voltage, temperature, and process variations. This paper proposes a new statistical performance analysis model for asynchronous pipelines. This model can be applied to two different styles of asynchronous circuits. The results show that this model has reasonable accuracy on estimated mean delay (2% error on average) compared to detailed analysis carried out with low-level Monte Carlo (MC) circuit simulations.

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具有动态电压标度的捆绑数据异步电路的统计性能分析框架

随着对低功耗电子产品需求的增长，异步电路被认为是解决功耗问题的一个很好的替代方案。在异步电路中应用动态电压缩放（DVS）可以进一步提高其功率效率。然而，异步电路面临着挑战，例如考虑电压、温度和工艺变化的性能分析。本文提出了一种新的异步管道统计性能分析模型。该模型可应用于两种不同类型的异步电路。结果表明，与低阶蒙特卡罗（MC）电路仿真进行的详细分析相比，该模型对估计的平均延迟具有合理的精度（平均误差为2%）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.