Untangling the Low Accuracy of the Entangling Instruction Prefetcher

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-20 DOI:10.1109/LCA.2026.3676273

Vedant Kalbande;Biswabandan Panda;Alexandra Jimborean;Alberto Ros

引用次数: 0

Abstract

The Entangling Instruction Prefetcher (EIP) is a state-of-the-art mechanism designed to improve instruction-fetch timeliness. While earlier studies report an average prefetch accuracy of 72% and as high as 91%, more recent evaluations using different methodologies—most notably the gem5 simulator—report lower accuracies of 44% on average and even below 30%. This work aims to shed light on this controversy by providing a robust and faithful open-source implementation within the gem5 simulation framework. In addition, we analyze several design choices that influence EIP's accuracy and performance highlighting common pitfalls when porting EIP across simulators. In our experiments, using the same benchmarks as prior studies, our gem5 version of EIP achieves an average prefetch accuracy of 64.35%, demonstrating that its accuracy remains stable across the simulators.

查看原文本刊更多论文

解决缠结指令预取器精度低的问题

纠缠指令预取器（EIP）是一种先进的机制，旨在提高指令提取的及时性。虽然早期的研究报告平均预取准确率为72%，最高可达91%，但最近使用不同方法（最值得注意的是gem5模拟器）的评估报告平均准确率较低，为44%，甚至低于30%。这项工作旨在通过在gem5仿真框架内提供一个健壮和忠实的开源实现来阐明这一争议。此外，我们分析了几种影响EIP准确性和性能的设计选择，强调了跨模拟器移植EIP时的常见缺陷。在我们的实验中，使用与先前研究相同的基准测试，我们的gem5版本的EIP实现了64.35%的平均预取精度，表明其精度在模拟器中保持稳定。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.