Power-efficient 2:1 MUX and 1:2 DEMUX architectures in 90 NM technology using SVL and FinFET approaches

Abstract

Low power, high speed 2:1 MUX designs using static CMOS and pseudo NMOS logic are listed in this study together with 1:2 DEMUXes using pass transistor-based and CMOS-based DEMUXes. Compared with previous studies, which evaluated SVL or FinFET approaches singly, this study provides a comprehensive comparative examination of numerous logic styles—static CMOS, pseudo-NMOS, and pass-transistor—under identical simulation settings. The suggested methodology offers useful design insights for selecting low-power MUX/DEMUX designs in 90 nm technology. When applied to a 2:1 MUX architecture with pseudo NMOS and static CMOS logic, SVL (Supply Voltage Level) is one of the most important low power techniques that effectively lowers leakage power. The SVL operates by combining the functions of the Upper and Lower SVL circuits. By sending a base ground state voltage and a maximum supply voltage separately to the dynamic load circuit, SVL circuits can optimize the 2:1 MUX circuit’s operating speed. Upper and Lower SVL circuits are run concurrently in order to minimize leakage power in SVL circuits. FinFET (Fin Shaped Field Effect Transistor) technology are used to implement the 1:2 DEMUX using static CMOS logic, pass transistor logic. Optimal current, entry dielectric spillage, short channel effects, and device-to-device variations are the primary obstacles to expanding bulk CMOS gate lengths. In any case, designs based on FinFETs provide increased yield, reduced leakage, and improved power over short channel effects.