Triple metal gate vertical TFET with SiGe/Si heterojunction for high-performance and low-power VLSI circuits

Abstract

This paper presents a comprehensive simulation-based investigation of a Triple-Metal-Gate Vertical Tunnel Field-Effect Transistor (TMG-VTFET) on a doped silicon substrate and explores its potential for low-power analog and mixed-signal circuit applications. The proposed device employs a triple-segment gate, where the central segment is engineered with a higher work function as compared to the adjacent segments, forming an internal channel barrier that enables precise control of the band-to-band tunneling mechanism while significantly suppressing ambipolar current. To further enhance tunneling efficiency and ON-state performance, a SiGe source pocket is incorporated. Detailed Silvaco ATLAS TCAD simulations reveal that the optimized SiGe-pocket TMG-VTFET (TMG-VTFET-WP) achieves a steep subthreshold swing below 12.40 mV/dec, an I_ON/I_OFF ratio exceeding 10¹⁴, and an ON-state current on the order of 10⁻⁴ A/µm—performance metrics that remarkably surpass those of the pocket-less counterpart. Circuit-level suitability is evaluated using Cadence, where the TMG-VTFET-WP is integrated into CMOS inverter and ring oscillator circuits; the results confirm robust DC characteristics, improved switching speed, and reliable transient response. Ultimately, the simulation-based results confirm that the SiGe-pocket TMG-VTFET (TMG-VTFET-WP) achieves exceptional device performance, making it a promising candidate for energy-efficient integration in future analog and digital system designs.