{"title":"All-optical AND Logic Gate With High Extinction Ratio for Neural Network Hardware Implementation","authors":"Rita Asquini;Alessio Buzzin;Badrul Alam;Andrea Ceschini;Antonello Rosato;Massimo Panella","doi":"10.1109/JETCAS.2025.3623865","DOIUrl":null,"url":null,"abstract":"The development of optical logic gates suitable for multi-stage processes is a central issue in emerging computational applications such as optical neural networks. In this work, we introduce and analyze a scheme for an all-optical AND logic gate, which allows achieving an almost ideal extinction ratio, a feature that simplifies cascaded architectures for complex operations such as multibit sums and multiplications. We analytically demonstrate how our scheme forces three logical states, namely ‘00’, ‘11’ and ‘10’, to be necessarily ideal in behavior. We also outline the conditions for ideal behavior of the remaining logical state ‘01’, which requires the use of semiconductor optical amplifiers (SOA) in their non-linear operations, by tuning the optical input and feeding current. Our numerical analysis on symmetrically balanced SOAs shows that there are multiple conditions enabling a very small output at logical ‘01’; also, our results suggest that those solutions are strongly influenced by the phase shifts induced in SOAs, which requires to avoid small <inline-formula> <tex-math>$\\alpha $ </tex-math></inline-formula> factors. The performance outlined in our transitions are promising for the implementation of universal gates to be deployed in future architectures for neural optical computation.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"106-114"},"PeriodicalIF":3.8000,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11208673/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The development of optical logic gates suitable for multi-stage processes is a central issue in emerging computational applications such as optical neural networks. In this work, we introduce and analyze a scheme for an all-optical AND logic gate, which allows achieving an almost ideal extinction ratio, a feature that simplifies cascaded architectures for complex operations such as multibit sums and multiplications. We analytically demonstrate how our scheme forces three logical states, namely ‘00’, ‘11’ and ‘10’, to be necessarily ideal in behavior. We also outline the conditions for ideal behavior of the remaining logical state ‘01’, which requires the use of semiconductor optical amplifiers (SOA) in their non-linear operations, by tuning the optical input and feeding current. Our numerical analysis on symmetrically balanced SOAs shows that there are multiple conditions enabling a very small output at logical ‘01’; also, our results suggest that those solutions are strongly influenced by the phase shifts induced in SOAs, which requires to avoid small $\alpha $ factors. The performance outlined in our transitions are promising for the implementation of universal gates to be deployed in future architectures for neural optical computation.
期刊介绍:
The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.