Fault modeling, testing, and repair for chiplet interconnects

Abstract

With the continuous advancement of semiconductor technology, chiplet technology has gained importance due to its significant advantages in enhancing performance, reducing power consumption, and saving space. However, vertical interconnect structures in 3D integrated circuits (ICs), such as through-silicon via (TSV) and inter-layer via (ILV), present unprecedented challenges in modeling, testing, and repair. This paper focuses on four modules: modeling for faults, TSV testing, ILV testing, and repair strategies. First, different methods of establishing TSV fault models and discussions on the influence of different defects on performance are introduced. Then, the challenges in detecting various faults of TSVs, such as short, delay faults, and crosstalk, and the presented corresponding testing methods are analyzed. Meanwhile, some electric parameter test methods are also discussed. In the ILV testing technology, the difficulties caused by the small size and high density of ILVs, which make traditional testing methods less effective, are discussed. Various testing and optimization methods are explored, aimed at improving fault coverage while minimizing testing time and hardware overhead. Moreover, repair strategies based on redundant TSVs are analyzed in this paper. Redundant repair architectures, including ring-based, honeycomb, and so on, are introduced. Additionally, the paper explores dynamic real-time fault-repair methods, such as time-division multiple access and online repair technologies, which aim to enhance the reliability and lifespan of 3D ICs. In conclusion, a comprehensive solution for the testing of 3D chiplet is presented.