A high-efficiency CMOS rectifier with wide dynamic range based on dual dynamic gate-biasing and body self-biasing techniques

Abstract

This paper presents an efficient CMOS rectifier with a wide PDR for radio-frequency energy harvesting (RFEH) applications. The proposed circuit employs a dual dynamic gate-biasing technique to enhance the forward current at low input power levels while suppress the reversed leakage current at high input power levels. Thus, the rectifier’s PDR can be extended. In addition, a body self-biasing technique is developed to reduce the rectifying transistors’ threshold voltage during conduction, which further improves the sensitivity and expands the PDR. For validation, a 200 MHz CMOS rectifier is designed in a 40 nm CMOS process. The rectifier occupies a $69\mu m$ × $93\mu m$ chip area. The post-simulation results show that the proposed rectifier achieves a 87.5% peak PCE, a -19.4 dBm sensitivity and a 25.2 dB PDR (for PCE$>$40%) with a 100 k$\Omega$ load.