Performance enhanced current-steering DAC using distributed dual randomization dynamic element matching technique

Abstract

The high-speed digital-to-analog-converters (DACs) mainly suffer from low dynamic performances due to mismatch induced non-linearities. The amplitude mismatch and timing mismatch are the major sources that critically challenge the DAC linearity at higher sampling frequencies. This article presents a 500 MHz 10-bit current-steering DAC (CS-DAC) that adopts distributed dual randomization Dynamic Element Matching (DDR-DEM) technique to address these challenges. The DDR-DEM CSDAC utilizes the advantage of distributed architecture to reduce the mid-code glitches. The dual randomization technique adds an additional degree of random rotation to suppress the non-linear distortion for high frequency DACs. The proposed architecture is designed in 180 nm CMOS process and occupies an area of 0.28 mm${}^2$. Monte-Carlo analysis shows this DAC achieves 71.6-dB spurious-free dynamic range (SFDR) at the near Nyquist the frequency range. The power consumption of the proposed DDRDEM CS-DAC is observed approximately 21.2 mW from 1.8 V DC supply.