Tiedong Cheng , Minghao Lai , Ziliang Wang , Xiao Wang
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引用次数: 0
Abstract
This paper presents a capacitor-less low-dropout regulator (LDO) for digital loads, featuring fast transient response and wide load range. To improve both the loop gain of the LDO and the slew rate at the gate of the power transistor, a high-slew-rate error amplifier is adopted. Furthermore, a push-pull dynamic capacitor frequency compensation strategy is proposed, which incorporates an embedded compensation capacitor (Cf2) to generate a left-half-plane (LHP) zero for improved stability. Working in conjunction with an auxiliary flipped-voltage-follower based transient enhancement circuit, the compensation strategy collectively enhances the transient performance. Designed in a 180 nm CMOS process, the proposed LDO achieves a maximum load current of 100 mA, a load capacitance range of 0–4 nF, and a dropout voltage of 200 mV, while maintaining a quiescent current of only 49.7 μA. Under 1.7 V supply with 50 μA-100 mA load current and 100 pF load capacitance, the circuit demonstrates 120 mV/620 ns (overshoot) and 170 mV/140 ns (undershoot) performance. The maximum load regulation and line regulation are 14.81 μV/mA and 2.917 mV/V, respectively.
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