Voltage controlled ring oscillator with multi-frequency shift keying technique for jitter reduction in 180 nm CMOS technology

Abstract

This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO) with an enhancement in the linearity range of VCRO by many folds. The proposed technique is helpful in VCRO-based analog-to-digital converters (ADC), Phase Locked Loop (PLL), and time-based circuits, where the jitter accumulation of VCRO severely degrades performance. In the proposed technique, a 4-bit vernier time-to-digital converter (VTDC) is used to extract jitter in terms of 4-bit thermometer code (TC) with a sensitivity of 10 ps/bit. The 4-bit thermometer code is input to a multi-frequency shift keying (M-FSK) bit generator to tune the frequency of VCRO for reducing jitter, and in this way the complexity of the thermometer to binary code converter circuit is bypassed. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply and occupies an area of 89.59 × 79 μm². After enabling the proposed technique, the RMS jitter reduces from 125.95 ps to 76.125 ps for VCRO running at 76.08 MHz and consumes a total power of 1.6mW with FOM of -202.276 dB.