CTL: A Case for CXL Device-Managed Hugepages

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-02-06 DOI:10.1109/LCA.2026.3661563

Sangbeom Jeon;Sang-Hoon Kim

引用次数: 0

Abstract

Compute Express Link (CXL) enables memory expansion via high-speed cache-coherent interconnects, yet it magnifies address translation overheads due to limited TLB reach. While hugepages alleviate translation costs, they introduce severe fragmentation and compaction overheads in long-running systems. Given this trade-off, we propose the CXL Translation Layer (CTL), a device-resident mechanism that provides host with hugepages using fine-grained basepages in the device. CTL preserves the hugepage-level translation efficiency while achieving flexible memory management, delivering near-native performance in ideal cases and up to 16% improvement under fragmented conditions.

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CTL: CXL设备管理大页面的案例

计算快速链路（Compute Express Link， CXL）通过高速缓存一致互连实现内存扩展，但由于TLB覆盖范围有限，它放大了地址转换开销。虽然大页面减轻了翻译成本，但它们在长时间运行的系统中引入了严重的碎片和压缩开销。考虑到这种权衡，我们提出了CXL转换层（CTL），这是一种设备驻留机制，它使用设备中的细粒度基页为主机提供巨大的页面。CTL保留了巨大的页面级翻译效率，同时实现了灵活的内存管理，在理想情况下提供接近本机的性能，在碎片化条件下提供高达16%的改进。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.