Driving the Core Frontend With LiteBTB

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Roman K. Brunner;Rakesh Kumar
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Abstract

Branch target buffer (BTB) is a central component of high performance core front-ends as it not only steers instruction fetch by uncovering upcoming control flow but also enables highly effective fetch-directed instruction prefetching. However, the massive instruction footprints of modern server applications far exceed the capacities of moderately sized BTBs, resulting in frequent misses that inevitably hurt performance. While commercial CPUs deploy large BTBs to mitigate this problem, they incur high storage and area overheads. Prior efforts to reduce BTB storage have primarily targeted branch targets, which has proven highly effective — so much that the tag storage now dominates the BTB storage budget. We make a key observation that BTBs exhibit a large degree of tag redundancy, i.e. only a small fraction of entries contain unique tags, and this fraction falls sharply as BTB capacity grows. Leveraging this insight, we propose LiteBTB, which employs a dedicated hardware structure to store unique tags only once and replaces per-entry tags in BTB with compact tag pointers. To avoid latency overheads, LiteBTB accesses the tag storage and BTB in parallel. Our evaluation shows that LiteBTB reduces storage by up to 13.1% compared to the state-of-the-art BTB design, called BTB-X, while maintaining equivalent performance. Alternatively, with the same storage budget, LiteBTB accommodates up to 1.125× more branches, yielding up to 2.7% performance improvement.
用LiteBTB驱动核心前端
分支目标缓冲区(BTB)是高性能核心前端的核心组件,它不仅通过揭示即将到来的控制流来引导指令提取,而且还实现了高效的定向提取指令预取。然而,现代服务器应用程序的大量指令占用远远超过中等大小的btb的容量,导致频繁的错误,这不可避免地会损害性能。虽然商用cpu部署了大型btb来缓解这个问题,但它们会产生很高的存储和区域开销。先前减少BTB存储的努力主要针对分支目标,这已被证明是非常有效的——以至于标签存储现在主导了BTB存储预算。我们观察到BTB表现出很大程度的标签冗余,即只有一小部分条目包含唯一标签,并且随着BTB容量的增长,这一比例急剧下降。利用这种见解,我们提出了LiteBTB,它使用专用的硬件结构只存储唯一标签一次,并用紧凑的标签指针替换BTB中的每个条目标签。为了避免延迟开销,LiteBTB并行访问标签存储和BTB。我们的评估表明,与最先进的BTB设计(称为BTB- x)相比,LiteBTB最多可减少13.1%的存储空间,同时保持相同的性能。或者,在相同的存储预算下,LiteBTB可以容纳多达1.125倍的分支,从而产生高达2.7%的性能提升。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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