SAP: Shared-Aware Prefetching for Reducing Inter-Chiplet Data Access Latency

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Junpei Huang;Haobo Xu;Yiming Gan;Ying Li;Wenhao Sun;Mengdi Wang;Xiaotong Wei;Feng Min;Ying Wang;Yinhe Han
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引用次数: 0

Abstract

In multi-chiplet systems, inter-chiplet shared-data transfers pose a significant bottleneck, prolonging the critical paths of memory accesses. In inter-chiplet coherence traffic, since each chiplet often needs to wait reactively for data from remote chiplets, proactive data-fetching mechanisms such as prefetching are essential to anticipate inter-chiplet data accesses and mitigate latency. Nevertheless, traditional prefetchers are inadequate for explicitly handling inter-chiplet shared-data transfers, overlooking potential prefetching opportunities. To overcome this limitation, we propose SAP, a shared-aware prefetching mechanism that minimizes inter-chiplet data access latency. By transforming the IO chiplet into an active prefetching agent, SAP proactively fetches inter-chiplet shared data before demand requests arrive, utilizing a sharing table to track recent shared-data events and a prefetch agent to initiate inter-chiplet data transfers early. Our experiments on a chiplet-based system demonstrate that SAP improves system throughput by 13.44% and reduces execution time by 12.33% compared to the prior design.
SAP:共享感知预取,减少片间数据访问延迟
在多晶片系统中,晶片间的共享数据传输成为一个重要的瓶颈,延长了内存访问的关键路径。在芯片间相干通信中,由于每个芯片通常需要被动地等待来自远程芯片的数据,因此预取等主动数据获取机制对于预测芯片间数据访问和减轻延迟至关重要。然而,传统的预取器不足以显式处理芯片间的共享数据传输,忽略了潜在的预取机会。为了克服这一限制,我们提出了SAP,这是一种共享感知的预取机制,可以最大限度地减少芯片间数据访问延迟。通过将IO芯片转换为主动预取代理,SAP在需求请求到达之前主动获取芯片间共享数据,利用共享表跟踪最近的共享数据事件,并利用预取代理提前启动芯片间数据传输。我们在基于芯片的系统上的实验表明,与之前的设计相比,SAP提高了13.44%的系统吞吐量,减少了12.33%的执行时间。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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