DAWN: Efficient Distribution of Attention Workload in PIM-Enabled Systems for LLM Inference

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jaehoon Chung;Jinho Han;Young-Ho Gong;Sung Woo Chung
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引用次数: 0

Abstract

Recently, processing-in-memory (PIM) units have been deployed to accelerate matrix-vector multiplications in large language models (LLMs). However, due to the limited flexibility of PIMs, PIMs require a strict data layout for storing matrices in memory. As LLM inference operates autoregressively, new elements are appended to the stored matrices during inference, necessitating costly data layout reorganization. Nevertheless, since the conventional workload allocation method assigns entire matrices solely to PIMs, it causes data layout reorganization overhead (i.e., excessive memory writes). Furthermore, the significant variance in matrix sizes exacerbates PIM load imbalance. In this letter, we propose DAWN, a novel workload allocation method. DAWN divides matrices into equally sized chunks and employs a single chunk as the allocation unit. DAWN assigns a portion of chunks to traditional accelerators (e.g., neural processing units), which have no constraints on data layout for computation, to mitigate reorganization overhead. DAWN evenly distributes the remaining chunks across PIMs using a greedy approach to achieve PIM load balancing. Our simulation results show that DAWN improves throughput by up to 44.2% (34.8% on average) over the conventional workload allocation method.
在支持pim的LLM推理系统中有效分配注意力工作量
最近,内存处理(PIM)单元被用于加速大型语言模型(llm)中的矩阵向量乘法。然而,由于pim的灵活性有限,pim需要严格的数据布局才能在内存中存储矩阵。由于LLM推理操作是自回归的,在推理过程中,新元素被附加到存储的矩阵中,需要进行昂贵的数据布局重组。然而,由于传统的工作负载分配方法将整个矩阵单独分配给pim,因此会导致数据布局重组开销(即过多的内存写入)。此外,矩阵大小的显著差异加剧了PIM负载不平衡。在这封信中,我们提出了一种新的工作负载分配方法DAWN。DAWN将矩阵划分为大小相等的块,并使用单个块作为分配单元。DAWN将一部分数据块分配给传统的加速器(例如,神经处理单元),这些加速器对计算的数据布局没有限制,以减轻重组开销。DAWN使用贪婪的方法将剩余的块均匀地分布在PIM上,以实现PIM的负载平衡。我们的模拟结果表明,与传统的工作负载分配方法相比,DAWN将吞吐量提高了44.2%(平均34.8%)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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