Coupled effects of cracks and interfacial thermal resistance on heat conduction in flip-chip packages

Abstract

Thermal management in flip-chip packaging architectures constitutes a fundamental reliability concern in advanced microelectronic systems, where elevated junction temperatures precipitate accelerated degradation mechanisms and catastrophic device failure. This study presents a comprehensive thermal characterization of structurally compromised flip-chip assemblies through the implementation of a coupled peridynamic-differential algebraic equation (PD-DAE) computational framework. The employed formulation facilitates high-fidelity resolution of multiscale thermal transport phenomena, encompassing both transient non-equilibrium dynamics and steady-state heat dissipation, while rigorously accounting for interfacial thermal boundary resistance and crack-induced thermal discontinuities. The results show that the interfacial thermal resistance (ITR) adjacent to the chip dominates the junction temperature: increasing $R_1$(chip-lid interface resistance) from 0 to 2 mm${}^2\cdot$K$\cdot$W⁻¹ raises the maximum chip temperature from 73.8 °C to 83.3 °C, while variations in $R_2$(lid-heat sink interface resistance) have limited influence. The transient analysis reveals distinct non-Fourier thermal wave propagation and interface-induced reflection and transmission, with the chip temperature rising from 28.8 °C to 72.4 °C within 0.3 s before stabilizing at 77.2 °C. Crack defects are shown to hinder vertical heat flow and cause localized overheating, increasing the junction temperature by up to 5.2 °C, while internal cracks within the silicon induce an additional 6 °C rise compared with interfacial cracks. Moreover, an optimal thermal interface material (TIM) thickness of 0.15-0.20 mm achieves the lowest junction temperature, reducing it from 83.8 °C to 68.3 °C through improved interfacial conformity. Overall, the study highlights that interfacial characteristics, crack defects, and TIM configuration jointly dictate the thermal reliability of flip-chip assemblies. The proposed peridynamic–non-Fourier framework provides a robust tool for analyzing damage-induced thermal degradation and guiding the design of next-generation microelectronic packaging with enhanced heat dissipation and reliability.