MORL-IC: Multi-objective reinforcement learning approaches for analog integrated circuits optimization

IF 2.6 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-19 DOI:10.1016/j.vlsi.2026.102664
Hakan Taşkıran, Engin Afacan
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引用次数: 0

Abstract

Analog and RF integrated circuit (IC) design requires the simultaneous optimization of multiple, conflicting objectives under highly nonlinear and tightly coupled constraints. While prior studies — including our own — have demonstrated the feasibility of applying multi-objective reinforcement learning (MORL) to analog circuit optimization, the specific impact of workflow-level design choices on convergence behavior, simulation cost, and Pareto-front characteristics has remained insufficiently explored. This paper reformulates the Multi-Objective Deep Deterministic Policy Gradient (MODDPG) approach not as a single fixed algorithm, but as a family of optimization workflows that share an identical multi-objective actor–critic learning core while systematically differing in their initialization strategy and environment evaluation mechanism. Within this unified formulation, three configurations are investigated: (i) a baseline MODDPG workflow with random initialization and direct SPICE evaluation, (ii) MODDPG-2, which employs analytically derived extreme solutions to guide early exploration, and (iii) MODDPG-3, which introduces an ANN-based pseudo-designer to generate boundary solutions directly from performance specifications. In addition, a Fully-ANN execution mode is examined, where an ANN-based pseudo-simulator replaces SPICE during policy learning to accelerate environment interaction. By preserving the same reinforcement learning architecture across all variants, the proposed framework isolates the effects of structured initialization and surrogate-based environments on optimization outcomes. The workflows are evaluated on three analog circuits (active-loaded differential amplifier, folded-cascode amplifier, and voltage comparator) and one RF circuit (CMOS cross-coupled LC oscillator), as well as on standard analytical benchmarks. Comparative results against NSGA-II and MOEA/D show that no single method universally dominates; however, the proposed workflows consistently reduce the number of required SPICE simulations by approximately 30%–75% while maintaining competitive Pareto-front quality. This efficiency gain indicates that the reinforcement-learning agent progressively acquires design intuition comparable to that of an experienced human designer—learning to avoid unpromising regions of the design space and focusing evaluations on high-value candidates. The results therefore demonstrate that, beyond the choice of learning algorithm, workflow-level design decisions critically shape how effectively RL can emulate expert design behavior, offering practical guidance for balancing solution quality and computational cost in automated analog and RF circuit design flows.
模拟集成电路优化的多目标强化学习方法
模拟和射频集成电路(IC)设计需要在高度非线性和紧密耦合约束下同时优化多个相互冲突的目标。虽然之前的研究(包括我们自己的研究)已经证明了将多目标强化学习(MORL)应用于模拟电路优化的可行性,但工作流级设计选择对收敛行为、仿真成本和帕累托前特征的具体影响仍然没有得到充分的探讨。本文将多目标深度确定性策略梯度(MODDPG)方法重新表述为一组优化工作流,而不是单一的固定算法,这些工作流共享相同的多目标行为者-批评者学习核心,但在初始化策略和环境评估机制上存在系统差异。在这个统一的公式中,研究了三种配置:(i)随机初始化和直接SPICE评估的基线MODDPG工作流,(ii) MODDPG-2,它采用解析导出的极值解来指导早期探索,以及(iii) MODDPG-3,它引入了基于人工神经网络的伪设计器,直接从性能规范生成边界解。此外,研究了全神经网络执行模式,其中基于神经网络的伪模拟器在策略学习期间取代SPICE以加速环境交互。通过在所有变量中保留相同的强化学习架构,所提出的框架隔离了结构化初始化和基于代理的环境对优化结果的影响。工作流程在三个模拟电路(有源负载差分放大器、折叠级联放大器和电压比较器)和一个射频电路(CMOS交叉耦合LC振荡器)以及标准分析基准上进行了评估。与NSGA-II和MOEA/D的比较结果表明,没有一种方法具有普遍的优势;然而,所提出的工作流程始终如一地将所需SPICE模拟的数量减少了大约30%-75%,同时保持了具有竞争力的Pareto-front质量。这种效率增益表明,强化学习代理逐渐获得了与经验丰富的人类设计师相当的设计直觉——学习避免设计空间中没有希望的区域,并将评估集中在高价值的候选对象上。因此,结果表明,除了学习算法的选择之外,工作流级设计决策对强化学习如何有效地模拟专家设计行为至关重要,为在自动化模拟和射频电路设计流程中平衡解决方案质量和计算成本提供了实用指导。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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