{"title":"Behavioural Modelling and Verification of a Novel Weighted System-Level Chopping for High-Resolution Incremental ADCs","authors":"Woosol Han, Keonhee Sim, Taehoon Kim, Jaehoon Jun","doi":"10.1049/ell2.70497","DOIUrl":null,"url":null,"abstract":"<p>The system-level chopping (SLC) technique attenuates low-frequency noise, such as 1/<i>f</i> noise, particularly in an incremental analogue-to-digital converter (IADC). To achieve additional low-frequency noise attenuation, SLC can be utilised together with dynamic offset cancellation (DOC) techniques such as correlated double sampling (CDS) and auto-zeroing (AZ). In this letter, a novel weighted system-level chopping (WSLC) technique is proposed to achieve a further suppressed low-frequency noise characteristic. By applying the proposed WSLC with a dynamic circuit weight, a third-order high-pass noise transfer function (NTF) can be achieved efficiently. Consequently, with the noise weight of 0.9, it provides a 1/<i>f</i> noise suppression of 78.94% compared to the conventional second-order SLC technique while maintaining the same ADC latency.</p>","PeriodicalId":11556,"journal":{"name":"Electronics Letters","volume":"62 1","pages":""},"PeriodicalIF":1.0000,"publicationDate":"2026-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/ell2.70497","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics Letters","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/ell2.70497","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The system-level chopping (SLC) technique attenuates low-frequency noise, such as 1/f noise, particularly in an incremental analogue-to-digital converter (IADC). To achieve additional low-frequency noise attenuation, SLC can be utilised together with dynamic offset cancellation (DOC) techniques such as correlated double sampling (CDS) and auto-zeroing (AZ). In this letter, a novel weighted system-level chopping (WSLC) technique is proposed to achieve a further suppressed low-frequency noise characteristic. By applying the proposed WSLC with a dynamic circuit weight, a third-order high-pass noise transfer function (NTF) can be achieved efficiently. Consequently, with the noise weight of 0.9, it provides a 1/f noise suppression of 78.94% compared to the conventional second-order SLC technique while maintaining the same ADC latency.
期刊介绍：
Electronics Letters is an internationally renowned peer-reviewed rapid-communication journal that publishes short original research papers every two weeks. Its broad and interdisciplinary scope covers the latest developments in all electronic engineering related fields including communication, biomedical, optical and device technologies. Electronics Letters also provides further insight into some of the latest developments through special features and interviews.
Scope
As a journal at the forefront of its field, Electronics Letters publishes papers covering all themes of electronic and electrical engineering. The major themes of the journal are listed below.
Antennas and Propagation
Biomedical and Bioinspired Technologies, Signal Processing and Applications
Control Engineering
Electromagnetism: Theory, Materials and Devices
Electronic Circuits and Systems
Image, Video and Vision Processing and Applications
Information, Computing and Communications
Instrumentation and Measurement
Microwave Technology
Optical Communications
Photonics and Opto-Electronics
Power Electronics, Energy and Sustainability
Radar, Sonar and Navigation
Semiconductor Technology
Signal Processing
MIMO
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