Qianwei Yu , Pengbo Nie , Zihan Wang , Chengcheng Wan , Ziyi Lin , He Jiang , Jianjun Zhao , Lei Qiao , Le Chen , Yuting Chen
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引用次数: 0
Abstract
With the emergence of the needs of edge computing, there arises a demand for training and inferring deep learning (DL) models on memory-constrained devices. However, many DL models, namely computation graphs, have complex structure and plenty of parameters, incurring heavy memory consumption at runtime. Hence it is challenging but necessary to reduce their memory footprints at runtime.
This paper proposes OPass, a novel approach to perform hierarchical memory-constrained operator scheduling of machine learning models, and orchestrate optimization passes of Apache’s TVM (a machine learning compilation framework) for lowering memory footprints of computation graphs, finally allowing the graphs to run on memory-constrained devices. Firstly, given a computation graph , OPass optimizes the graph heuristically and iteratively: OPass learns the effects of passes on the graph; it then optimizes iteratively — each iteration picks up a pass by the reduction of the memory footprint of and as well the implicit effects of the pass for further optimizations, letting the pass be applied. The second core component of OPass is its memory computation technique, named OPassMem, which hierarchically schedules ’s operators. It constructs a hierarchical computation graph and employs an iterative scheduling algorithm to progressively reduce memory footprints.
We evaluate OPass on ReBench (a suite of computation graphs) and two real-world models (Transformer and ResNet). The results show the strength of OPass: it reduces up to 90.83% of graph’s memory footprints, outperforming TVM’s default by 2.34. Specifically, pass orchestration and graph scheduling reduce memory footprints by up to 54.34% and 81%, respectively.
期刊介绍:
The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software.
Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.