ARAS: Adaptive low-cost ReRAM-based accelerator for DNNs

IF 5.3 2区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Journal of Systems Architecture Pub Date : 2026-03-01 Epub Date: 2025-12-20 DOI:10.1016/j.sysarc.2025.103668
Mohammad Sabri, Marc Riera, Antonio González
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引用次数: 0

Abstract

Processing Using Memory (PUM) accelerators have the potential to perform Deep Neural Network (DNN) inference by using arrays of memory cells as computation engines. Among various memory technologies, ReRAM crossbars show promising performance in computing dot-product operations in the analog domain. Nevertheless, the expensive writing procedure of ReRAM cells has led researchers to design accelerators whose crossbars have enough capacity to store the full DNN. Given the tremendous and continuous increase in DNN model sizes, this approach is unfeasible for some networks, or inefficient due to the huge hardware requirements. Those accelerators lack the flexibility to adapt to any given DNN model, facing an adaptability challenge.
To address this issue we introduce ARAS, a cost-effective ReRAM-based accelerator that employs an offline scheduler to adapt different DNNs to the resource-limited hardware. ARAS also overlaps the computation of a layer with the weight writing of several layers to mitigate the high writing latency of ReRAM. Furthermore, ARAS introduces three optimizations aimed at reducing the energy overheads of writing in ReRAM. Our key optimization capitalizes on the observation that DNN weights can be re-encoded to augment their similarity between layers, increasing the amount of bitwise values that are equal or similar when overwriting ReRAM cells and, hence, reducing the amount of energy required to update the cells. Overall, ARAS greatly reduces the ReRAM writing activity. We evaluate ARAS on a popular set of DNNs. ARAS provides up to 2.2× speedup and 45% energy savings over a baseline PUM accelerator without any optimization. Compared to a TPU-like accelerator, ARAS provides up to 1.5× speedup and 62% energy savings.
ARAS:用于深度神经网络的自适应低成本rram加速器
使用内存处理(PUM)加速器有可能通过使用存储单元阵列作为计算引擎来执行深度神经网络(DNN)推理。在各种存储技术中,ReRAM交叉棒在模拟域计算点积运算方面表现出良好的性能。然而,昂贵的ReRAM细胞写入过程促使研究人员设计出具有足够容量存储完整深度神经网络的加速器。考虑到DNN模型规模的巨大和持续增长,这种方法对于某些网络是不可行的,或者由于巨大的硬件要求而效率低下。这些加速器缺乏适应任何给定DNN模型的灵活性,面临适应性挑战。为了解决这个问题,我们引入了ARAS,这是一种经济高效的基于reram的加速器,它采用离线调度器来适应不同的dnn以适应资源有限的硬件。ARAS还将一个层的计算与多个层的权重写入重叠,以减轻ReRAM的高写入延迟。此外,ARAS引入了三种优化,旨在减少在ReRAM中写入的能量开销。我们的关键优化利用了DNN权重可以被重新编码以增加层之间的相似性的观察结果,增加了覆盖ReRAM单元时相等或相似的位值的数量,从而减少了更新单元所需的能量。总的来说,ARAS大大减少了ReRAM写入活动。我们在一组流行的dnn上评估ARAS。在没有任何优化的情况下,与基准PUM加速器相比,ARAS提供高达2.2倍的加速和45%的节能。与类似tpu的加速器相比,ARAS提供高达1.5倍的加速和62%的节能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Journal of Systems Architecture
Journal of Systems Architecture 工程技术-计算机:硬件
CiteScore
8.70
自引率
15.60%
发文量
226
审稿时长
46 days
期刊介绍: The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software. Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.
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