CrossFetch: A Prefetching Scheme for Cross-Page Prefetching in the Physical Address Space

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Qi Shao;Per Stenstrom
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引用次数: 0

Abstract

Prefetching is an important technique to reduce the miss penalty in deep memory hierarchies, employing multiple levels of cache and memory. Unfortunately, state-of-the-art techniques avoid prefetching across page boundaries in physically addressed memory because contiguous virtual pages are not guaranteed to map to contiguous physical pages. Apart from low accuracy, prefetching across page boundaries can break protection domains, opening up security vulnerabilities. This paper proposes CrossFetch — the first prefetching technique that accurately and securely prefetches data across physical page boundaries. It uses a simple and novel translation mechanism that combines a conventional TLB, called forward TLB (FTLB), with a reverse TLB (RTLB) that provides mappings of physical pages to virtual. CrossFetch leverages a conventional Page Table Walker invoked by a conventional TLB to load mappings into the FTLB and RTLB. The paper demonstrates how CrossFetch can hide far-memory misses in hybrid main-memory systems and last-level cache misses. We show that CrossFetch can improve IPC by 5.7% (up to 27.7%) compared to intra-page prefetchers on SPEC2017 benchmarks where the tolerance of far-memory misses dominates.
交叉取:一种在物理地址空间中进行跨页预取的预取方案
预取是一种重要的技术,可以减少深度内存层次结构中丢失的损失,它采用了多级缓存和内存。不幸的是,最先进的技术避免在物理寻址内存中跨页边界预取,因为不能保证连续的虚拟页映射到连续的物理页。除了准确性低之外,跨页面边界的预取可能会破坏保护域,从而导致安全漏洞。本文提出了CrossFetch——第一种准确、安全地跨物理页面边界预取数据的预取技术。它使用一种简单而新颖的转换机制,将传统的TLB(称为正向TLB (FTLB))与反向TLB (RTLB)结合起来,后者提供了物理页面到虚拟页面的映射。CrossFetch利用由常规TLB调用的常规Page Table Walker将映射加载到FTLB和RTLB中。本文演示了CrossFetch如何在混合主存系统和最后一级缓存丢失中隐藏远内存丢失。我们表明,与SPEC2017基准上的页内预取器相比,CrossFetch可以将IPC提高5.7%(最高27.7%),其中远内存丢失的容错性占主导地位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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