Iterative Layout-Aware Power, Thermal, and IR-Drop Co-Optimization: Ensuring Convergency in 3D-ICs

Abstract

Continuous scaling of integrated circuits and the adoption of 3D integration have significantly increased power density, creating critical challenges for thermal and power integrity. Rising power densities can trigger thermal runaway, negatively impacting device reliability and performance. This paper presents an electrothermal coupling framework built upon commercial Electronic Design Automation (EDA) tools, designed for precise iterative analysis of power, thermal and IR-drop characteristics in 2D and 3D configurations of a many-core RISCV SoC. The proposed framework automates iterative Power-Temperature (P-T) simulations to evaluate thermal convergence and potential thermal runaway scenarios in Memory-on-Logic (MoL) and Logic-on-Memory (LoM) stacked configurations. It identifies thermal hotspots, tracks their progression and evaluates various cooling strategies. Initial results indicate that the first P-T iteration provides up to 10% power savings in 3D due to a 11% wirelength reduction compared to 2D. However, by the fifth iteration, MoL power saving reduces to 4%, whereas LoM maintains the 10% saving. LoM exhibits a 6°C lower peak temperature compared to MoL under equivalent cooling conditions. Compared to 2D, the range of power densities (110 - $260~W/cm^{2}$ ) results in temperature variations of $-1^{\circ } C$ to $+3^{\circ } C$ in LoM. A $10^{\circ } C$ rise in temperature increases IR-drop by 11%; however, physical design-aware adjustments, such as a tighter Power Delivery Network (PDN) pitch, effectively reducing IR-drop by 54%, mitigating thermal impacts.