{"title":"Downscaling of Self-Aligned Double-Gate Oxide Semiconductor TFT for Ultrahigh-PPI Displays","authors":"Mengran Liu;Haohang Zeng;Wenlong Chen;Shengjie Yang;Qianpeng Zhang;Dongxiang Luo;Lei Li;Kuan-Chang Chang;Shengdong Zhang;Congwei Liao;Lei Lu","doi":"10.1109/OJID.2025.3637082","DOIUrl":null,"url":null,"abstract":"The demand for ultrahigh pixels per inch (PPI) displays has surged in emerging augmented reality (AR), virtual reality (VR), extended reality (XR) applications. The critical requirements of low power loss, long-term reliability, large size, cost-effectiveness, and precise brightness control essentially restrict the simplification of pixel circuits for ultrahigh PPI displays. The mass production of the complementary metal-oxide-semiconductor (CMOS) backplanes is hindered by the small die size and high cost, while the low temperature poly-silicon (LTPS) thin film transistor (TFT) backplanes are subjected to the severe channel shortening effect. In contrast, featured with low-cost, large-area, and decent electrical performance, oxide semiconductors (OS) offer reasonable room for ultrahigh PPI displays. This work experimentally demonstrated downscaled self-aligned double-gate (SADG) OS TFT through optimizing the gate insulator and passivation layer, and verified their potential in ultrahigh PPI displays. Compared with single-gate (SG) operation mode of the proposed SADG TFT with Al<sub>2</sub>O<sub>3</sub> gate insulator and passivation layer, higher on-current, steeper subthreshold swing (<italic>SS</i>) of 64 mV/dec, and smaller threshold voltage (<italic>V</i><sub>TH</sub>), accompanied by ultralow leakage current around 10<sup>-14</sup> A/μm, are achieved under double-gate (DG) mode. Besides, the SADG TFT exhibits linear dynamic <italic>V</i><sub>TH</sub> modulation and negligible shift of <italic>V</i><sub>TH</sub> under bias stress, which are respectively beneficial to the flexible current modulation and long-term reliability of pixel circuit for ultrahigh PPI displays. Finally, we proposed a 7T2C pixel circuit for Micro-LED display based on the SADG TFT with 475 nm gate length. The simulation results suggest that the proposed 7T2C pixel circuit exhibits PWM and PAM characteristics, with the pixel density expected to reach 2252 PPI. These attributes make the proposed SADG TFT a promising candidate for the ideal immersive near-eye display with both large panel size and ultrahigh PPI.","PeriodicalId":100634,"journal":{"name":"IEEE Open Journal on Immersive Displays","volume":"2 ","pages":"191-199"},"PeriodicalIF":0.0000,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267497","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal on Immersive Displays","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11267497/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The demand for ultrahigh pixels per inch (PPI) displays has surged in emerging augmented reality (AR), virtual reality (VR), extended reality (XR) applications. The critical requirements of low power loss, long-term reliability, large size, cost-effectiveness, and precise brightness control essentially restrict the simplification of pixel circuits for ultrahigh PPI displays. The mass production of the complementary metal-oxide-semiconductor (CMOS) backplanes is hindered by the small die size and high cost, while the low temperature poly-silicon (LTPS) thin film transistor (TFT) backplanes are subjected to the severe channel shortening effect. In contrast, featured with low-cost, large-area, and decent electrical performance, oxide semiconductors (OS) offer reasonable room for ultrahigh PPI displays. This work experimentally demonstrated downscaled self-aligned double-gate (SADG) OS TFT through optimizing the gate insulator and passivation layer, and verified their potential in ultrahigh PPI displays. Compared with single-gate (SG) operation mode of the proposed SADG TFT with Al2O3 gate insulator and passivation layer, higher on-current, steeper subthreshold swing (SS) of 64 mV/dec, and smaller threshold voltage (VTH), accompanied by ultralow leakage current around 10-14 A/μm, are achieved under double-gate (DG) mode. Besides, the SADG TFT exhibits linear dynamic VTH modulation and negligible shift of VTH under bias stress, which are respectively beneficial to the flexible current modulation and long-term reliability of pixel circuit for ultrahigh PPI displays. Finally, we proposed a 7T2C pixel circuit for Micro-LED display based on the SADG TFT with 475 nm gate length. The simulation results suggest that the proposed 7T2C pixel circuit exhibits PWM and PAM characteristics, with the pixel density expected to reach 2252 PPI. These attributes make the proposed SADG TFT a promising candidate for the ideal immersive near-eye display with both large panel size and ultrahigh PPI.