Downscaling of Self-Aligned Double-Gate Oxide Semiconductor TFT for Ultrahigh-PPI Displays

Mengran Liu;Haohang Zeng;Wenlong Chen;Shengjie Yang;Qianpeng Zhang;Dongxiang Luo;Lei Li;Kuan-Chang Chang;Shengdong Zhang;Congwei Liao;Lei Lu
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Abstract

The demand for ultrahigh pixels per inch (PPI) displays has surged in emerging augmented reality (AR), virtual reality (VR), extended reality (XR) applications. The critical requirements of low power loss, long-term reliability, large size, cost-effectiveness, and precise brightness control essentially restrict the simplification of pixel circuits for ultrahigh PPI displays. The mass production of the complementary metal-oxide-semiconductor (CMOS) backplanes is hindered by the small die size and high cost, while the low temperature poly-silicon (LTPS) thin film transistor (TFT) backplanes are subjected to the severe channel shortening effect. In contrast, featured with low-cost, large-area, and decent electrical performance, oxide semiconductors (OS) offer reasonable room for ultrahigh PPI displays. This work experimentally demonstrated downscaled self-aligned double-gate (SADG) OS TFT through optimizing the gate insulator and passivation layer, and verified their potential in ultrahigh PPI displays. Compared with single-gate (SG) operation mode of the proposed SADG TFT with Al2O3 gate insulator and passivation layer, higher on-current, steeper subthreshold swing (SS) of 64 mV/dec, and smaller threshold voltage (VTH), accompanied by ultralow leakage current around 10-14 A/μm, are achieved under double-gate (DG) mode. Besides, the SADG TFT exhibits linear dynamic VTH modulation and negligible shift of VTH under bias stress, which are respectively beneficial to the flexible current modulation and long-term reliability of pixel circuit for ultrahigh PPI displays. Finally, we proposed a 7T2C pixel circuit for Micro-LED display based on the SADG TFT with 475 nm gate length. The simulation results suggest that the proposed 7T2C pixel circuit exhibits PWM and PAM characteristics, with the pixel density expected to reach 2252 PPI. These attributes make the proposed SADG TFT a promising candidate for the ideal immersive near-eye display with both large panel size and ultrahigh PPI.
超高ppi显示用自对准双栅氧化半导体TFT的降尺度研究
在新兴的增强现实(AR)、虚拟现实(VR)、扩展现实(XR)应用中,对超高每英寸像素(PPI)显示器的需求激增。低功耗、长期可靠性、大尺寸、成本效益和精确的亮度控制等关键要求本质上限制了超高PPI显示器像素电路的简化。互补金属氧化物半导体(CMOS)背板由于模具尺寸小、成本高而阻碍了其量产,而低温多晶硅(LTPS)薄膜晶体管(TFT)背板则受到严重的通道缩短效应的影响。相比之下,氧化物半导体(OS)具有低成本、大面积和良好的电气性能,为超高PPI显示器提供了合理的空间。本工作通过优化栅极绝缘体和钝化层,实验证明了缩小尺寸的自排列双栅(SADG) OS TFT,并验证了其在超高PPI显示器中的潜力。与采用Al2O3栅极绝缘子和钝化层的单门工作模式相比,双栅极(DG)模式下的导通电流更高,亚阈值摆幅(SS)更陡(64 mV/dec),阈值电压(VTH)更小,漏电流约为10-14 A/μm。此外,SADG TFT在偏置应力下表现出线性动态VTH调制和可忽略的VTH移位,这分别有利于超高PPI显示器的柔性电流调制和像素电路的长期可靠性。最后,我们提出了一种基于栅极长度为475 nm的SADG TFT的微型led显示7T2C像素电路。仿真结果表明,所设计的7T2C像素电路具有PWM和PAM特性,像素密度有望达到2252 PPI。这些特性使所提出的SADG TFT成为具有大面板尺寸和超高PPI的理想沉浸式近眼显示器的有希望的候选者。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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