{"title":"An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming","authors":"Jinwei Xie, Yubin Zhu, Kaining Han, Jianhao Hu","doi":"10.1049/cds2/5773930","DOIUrl":null,"url":null,"abstract":"<p>The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)-based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal-to-noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024-point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256-point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.8000,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5773930","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2/5773930","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)-based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal-to-noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024-point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256-point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.
期刊介绍:
IET Circuits, Devices & Systems covers the following topics:
Circuit theory and design, circuit analysis and simulation, computer aided design
Filters (analogue and switched capacitor)
Circuit implementations, cells and architectures for integration including VLSI
Testability, fault tolerant design, minimisation of circuits and CAD for VLSI
Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs
Device and process characterisation, device parameter extraction schemes
Mathematics of circuits and systems theory
Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers