Bayesian-Optimization-Based Post-Silicon Offset-Cancelation Technique for Analog Multipliers

Abstract

This paper presents a software-controlled offset-cancelation technique for analog multipliers that relies on the Bayesian-optimization algorithm. The capability of the technique was investigated on a test multiplier, which was developed for future use in machine learning (ML) accelerators whose convergence is sensitive to process-variation-induced DC offsets. By adjusting the multiplier biasing voltages, the proposed Bayesian-optimization-based method was able to reduce the offset within ±1.8 mV from an uncorrected maximum offset of 10.6 mV. In addition to reducing offsets, the measurements of the 65-nm CMOS multiplier also showed an average linearity-error improvement of nearly 10%, from 12.2% prior to offset correction to 2.2% after correction. We demonstrate that the proposed offset correction improved the learning outcome accuracy for MNIST dataset digit classification from approximately 10% to 90%.