Low-Voltage Enhancement-Mode p-Type SnO TFTs enabled by Surface Passivation and High-κ Dielectric Integration

Abstract

Tin monoxide (SnO), with its high theoretical hole mobility, holds great promise as a p-type semiconductor for complementary metal-oxide semiconductor (CMOS) thin-film transistors (TFTs). However, its low thermal stability and tendency to oxidize into n-type SnO₂ have hindered practical device fabrication. Additionally, most reported SnO-TFTs operate in depletion mode and utilize low-κ SiO₂ gate dielectrics, resulting in high static power consumption and operating voltages. In this work, we systematically investigate the electrical evolution of p-type SnO films and TFTs by tuning the oxygen partial pressure (Opp) and annealing temperature. We demonstrate that an optimal Opp of 5% combined with annealing at 250 °C effectively suppresses the transformation of p-type SnO into n-type SnO₂, while yielding high device performance with a saturation mobility of 3.06 cm²/Vs, an on/off current ratio of 7.15 × 10², a threshold voltage of 18.41 V, and a subthreshold swing of 19.72 V/dec. Moreover, passivating the SnO film with a thin SiO₂ layer increases the channel resistance due to the added resistive path and decreases the carrier concentration by partially screening the gate electric field. This electrostatic modulation converts the TFT operation from depletion mode to enhancement mode, reducing static power dissipation and shifting the threshold voltage to -0.17 V. Finally, replacing the conventional 300 nm SiO₂ gate dielectric with a solution-processed 30 nm high-κ ZrO₂ layer significantly enhances the gate capacitance. This substitution reduces the operating voltages from V_GS = -50 V and V_DS = -50 V to V_GS = -5 V and V_DS = -5 V. These findings highlight the importance of synergistic control over the channel, dielectric, and interface engineering to achieve high-performance, low-power p-type SnO TFTs, opening new possibilities for advanced and energy-efficient electronic applications.