Xiangbin Du , Yanmei Kong , Yuxin Ye , Hangtian Zhu , Ruiwen Liu , Guohe Zhang , Shichang Yun , Binbin Jiao
{"title":"Dual-embedded cooling for thermoelectric coolers in electronics thermal management","authors":"Xiangbin Du , Yanmei Kong , Yuxin Ye , Hangtian Zhu , Ruiwen Liu , Guohe Zhang , Shichang Yun , Binbin Jiao","doi":"10.1016/j.applthermaleng.2025.128568","DOIUrl":null,"url":null,"abstract":"<div><div>Optimizing thermoelectric cooler (TECs) efficiency and cooling capacity requires minimizing the temperature difference between cold and hot sides. However, the parasitic thermal resistance induced by thermal interface materials in the conventional integration of TEC-based cooling systems elevates temperature difference, compromising their performance under rated power conditions. This study demonstrates a dual-embedded thermal module that integrates thermoelectric legs on the chip backside (serving as the TEC cold side) and embeds microfluidic channels into the substrate of hot side (functioning as the TEC hot side). A silicon test chip with integrated temperature sensors and heating functions was utilized to evaluate cooling performance. Compared to the TEC cooling module with conventional integration, the proposed design achieves a 33% enhancement in coefficient of performance (COP), a 61% reduction in total thermal resistance under equivalent cooling conditions, and a 47% decrease in the proportion of additional thermal resistance outside the TEC in the module. In addition, a prediction model was developed to quantify the impact of parasitic thermal resistance on the maximum achievable cooling power under varying loads. The dual-embedded cooling module demonstrates simultaneous enhancements of 66% in cooling power and 27.2% in temperature difference compared to conventional thermal solutions under equivalent thermal boundary conditions. This co-designed architecture eliminates thermal interface materials, slashing parasitic thermal resistance across heat transfer pathways, while bypassing complex heterogeneous integration challenges between TEC substrates and silicon chips, thereby ensuring reliable TEC performance maximization for high-flux electronics cooling.</div></div>","PeriodicalId":8201,"journal":{"name":"Applied Thermal Engineering","volume":"281 ","pages":"Article 128568"},"PeriodicalIF":6.9000,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Applied Thermal Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1359431125031606","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENERGY & FUELS","Score":null,"Total":0}
引用次数: 0
Abstract
Optimizing thermoelectric cooler (TECs) efficiency and cooling capacity requires minimizing the temperature difference between cold and hot sides. However, the parasitic thermal resistance induced by thermal interface materials in the conventional integration of TEC-based cooling systems elevates temperature difference, compromising their performance under rated power conditions. This study demonstrates a dual-embedded thermal module that integrates thermoelectric legs on the chip backside (serving as the TEC cold side) and embeds microfluidic channels into the substrate of hot side (functioning as the TEC hot side). A silicon test chip with integrated temperature sensors and heating functions was utilized to evaluate cooling performance. Compared to the TEC cooling module with conventional integration, the proposed design achieves a 33% enhancement in coefficient of performance (COP), a 61% reduction in total thermal resistance under equivalent cooling conditions, and a 47% decrease in the proportion of additional thermal resistance outside the TEC in the module. In addition, a prediction model was developed to quantify the impact of parasitic thermal resistance on the maximum achievable cooling power under varying loads. The dual-embedded cooling module demonstrates simultaneous enhancements of 66% in cooling power and 27.2% in temperature difference compared to conventional thermal solutions under equivalent thermal boundary conditions. This co-designed architecture eliminates thermal interface materials, slashing parasitic thermal resistance across heat transfer pathways, while bypassing complex heterogeneous integration challenges between TEC substrates and silicon chips, thereby ensuring reliable TEC performance maximization for high-flux electronics cooling.
期刊介绍:
Applied Thermal Engineering disseminates novel research related to the design, development and demonstration of components, devices, equipment, technologies and systems involving thermal processes for the production, storage, utilization and conservation of energy, with a focus on engineering application.
The journal publishes high-quality and high-impact Original Research Articles, Review Articles, Short Communications and Letters to the Editor on cutting-edge innovations in research, and recent advances or issues of interest to the thermal engineering community.