Mobility Overestimation in Thin-Film Transistors: Effects of Device Geometry and Fringe Currents

Abstract

Amorphous oxide semiconductor-based thin-film transistors (oxide TFTs) were first demonstrated in 2004. These devices offer numerous advantages, including low-temperature processing, high carrier mobility, and ultralow off-current. As a result, oxide TFTs have already been adopted for backplane technologies in modern flat-panel displays. Furthermore, their ultralow off-current has attracted considerable attention for next-generation DRAM applications. However, device reliability remains a critical challenge. In particular, gate bias stress instabilities such as negative bias temperature stress and positive bias temperature stress significantly hinder the advancement of high-mobility oxide TFTs beyond low-temperature polycrystalline silicon (LTPS) technology. Therefore, the evaluation of both field-effect mobility (FEM) and bias stability is essential for oxide TFTs. The absolute value of FEM is especially important when identifying candidate materials to replace LTPS. In this context, we have recently found that incorrect FEM evaluation methods have been widely used in numerous published studies. Such errors have resulted in overestimated FEM values, potentially compromising objective comparisons of materials and fabrication processes. This study clearly demonstrates, through both experimental data and simulation-analytical modeling, how and why FEM overestimation occurs. In particular, we derive a compact analytical expression based on conformal mapping and validate it using TCAD simulations and measurements. This dual-pronged approach establishes a general framework for identifying and correcting mobility overestimation. This study highlights the importance of recognizing and addressing mobility overestimation within the field, and that the proposed FEM evaluation method should be adopted to enable more objective and reliable comparisons.