A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs

IF 5.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-10-07 DOI:10.1109/jssc.2025.3613774

Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Youngsun Song, Chung-Ho Yu, Hirano Makoto, Yongseok Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Philkyu Kang, Byungrok Go, Minseok Kim, Seoyoon Jeon, Jaehwan Ryu, Jungmin Seo, Hwan-Seok Ku, Youngmin Jo, Doo-Hyun Kim, Hyunjun Yoon, Wontae Kim, Inmo Kim, Sunghoon Kim, Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Youngdon Choi, Il-Han Park, Chiweon Yoon, Hyunsuk Kim, Jaehoon Jang, Seungjae Lee, Ki-Whan Song, Sung-Hoi Hur

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一个28gb /mm2 4xx层1-Tb 3-b/Cell WF-Bonding 3D-nand闪存与5.6 gb /s/Pin IOs

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.