Low Latency Multikernel Polar Codes Using Approximate Processing Element

Abstract

Polar codes have become increasingly popular over the last few years and are currently adopted for the control channels in 5G wireless communication systems. However, the traditional polar codes use a (2 $\times$ 2) binary kernel, which limits codeword lengths to powers of 2. Multikernel polar codes were proposed to provide flexibility in terms of codeword lengths and are decoded using a successive cancellation (SC) decoder. This work presents the architecture of a low-latency SC decoder based on an approximate technique, decoding 3 bits in a single clock cycle at the final stage. The processing elements of the decoder are synthesized using the Synopsys design compiler in CMOS 32-nm technology. The processing element shows an average reduction of 53% in the area and 66.5% power savings. The proposed decoder's architecture is validated by FPGA implementation for a codeword length (768,384) and a code rate of 0.5. The proposed architecture demonstrates an effective hardware reduction technique with a significant decrease in the average latency of 51% and a minimal degradation in error performance, making it suitable for video broadcasting applications in 5G communications.