Placement and routing method based on picosecond time-to-digital converter

Abstract

The Time-to-Digital Converter (TDC) is a precise time-measuring device utilized for the accurate measurement of time intervals. It finds extensive applications in nuclear science, medicine, precision instrumentation, and various other fields. The measurement precision and resolution of a TDC are critical parameters that significantly influence the overall performance of the system. This article presents an implementation scheme for a TDC based on Field-Programmable Gate Arrays (FPGA). Additionally, considering the underlying hardware architecture of FPGAs, it highlights potential placement and routing issues that may arise during the design process of the FPGA-based TDC and conducts a corresponding theoretical analysis and design implementation to address these issues. Furthermore, this study focuses on designing a control experiment to investigate the relationship between the clock paths of each register and the externally input trigger signals, as well as the data input pins of each register. Based on the average values of three Time Delay Lines (TDLs), it is observed that when two different clock placement and routing methods are employed for the TDL, the difference in sampling time ranges is 54.334 ps, while the difference in TDL resolutions is 0.047 ps. This investigation emphasizes the importance of clock path design in optimizing TDC performance.