Optimizing n+ poly-Si layer doping and plasma treatments for enhanced electrical and thickness uniformity in n-type c-Si wafers

IF 4.2 Q2 CHEMISTRY, MULTIDISCIPLINARY
Hasnain Yousuf , Muhammad Quddamah Khokhar , Alamgeer , Mengmeng Chu , Rafi ur Rahman , Maha Nur Aida , Donghyun Oh , Youngkuk Kim , Junsin Yi
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引用次数: 0

Abstract

This study investigates n+ polycrystalline silicon (poly-Si) layers, focusing on doping concentration and post-deposition treatments, to understand their electrical and structural properties on n-type crystalline silicon wafers. To address challenges in conductivity and film uniformity, the PH3/SiH4 gas ratio (1.2–4.0) was varied during PECVD deposition, followed by high-temperature annealing and selective NH3 plasma exposure. Amorphous silicon (a-Si:H) was first deposited (on ultrathin SiOx for optical-uniformity mapping) and subsequently crystallized into n+ poly-Si by annealing at 900 °C. Post-treatments (HF dip, NH3 plasma) were then applied. Increasing dopant ratio raised carrier concentration (n) from 1.4 × 1020 to 3.16 × 1020 cm−3 while decreasing resistivity (ρ) and sheet resistance (Rs). Zone-dependent variations were evident across the 8-zone PECVD: Zone 4 generally exhibited lower Rs and higher μ, whereas Zone 8 lagged. Annealing improved crystallinity and electrical uniformity; NH3 plasma, used here as a surface treatment on the poly-Si layer (not a full passivating-contact stack), produced a small increase in Rs that indicates the need for further plasma-parameter tuning for uniform electrical outcomes. Raman and ellipsometry confirmed crystallinity (Xc) and thickness distributions consistent with transport trends. This work focuses on layer-level optimization of n+ poly-Si; surface passivation quality and contact resistivity (ρc) of complete poly-Si/SiOx stacks are not evaluated and will be addressed in future work. For electrical characterization, Hall parameters (n, μ) were extracted using glass-surrogate structures to avoid substrate conduction, and Rs was measured on wafers by four-point probe. The optimized layers are intended for rear-side electron-selective contacts in conventional n-type TOPCon, where optical penalties are modest; front-side use would require additional thickness minimization and optical re-optimization.

Abstract Image

优化n+多晶硅层掺杂和等离子体处理以增强n型c-Si晶圆的电性和厚度均匀性
本研究研究了n+多晶硅(poly-Si)层,重点关注掺杂浓度和沉积后处理,以了解其在n型多晶硅片上的电学和结构性能。为了解决电导率和薄膜均匀性的问题,在PECVD沉积过程中改变PH3/SiH4气体比(1.2-4.0),然后进行高温退火和选择性NH3等离子体暴露。非晶硅(a-Si:H)首先沉积(在超薄SiOx上进行光学均匀性映射),随后在900°C下退火结晶成n+多晶硅。然后进行后处理(HF浸提,NH3等离子体)。随着掺杂比的增加,载流子浓度(n)从1.4 × 1020增加到3.16 × 1020 cm−3,电阻率(ρ)和片电阻(Rs)降低。8区PECVD存在明显的区相关差异,4区普遍表现出较低的Rs和较高的μ,而8区滞后。退火改善了结晶度和电均匀性;NH3等离子体在这里用作多晶硅层(不是完全钝化接触堆栈)的表面处理,产生了Rs的小幅增加,这表明需要进一步调整等离子体参数以获得均匀的电结果。拉曼和椭偏仪证实结晶度(Xc)和厚度分布与输运趋势一致。本文主要研究n+多晶硅的层级优化;完整的多晶硅/SiOx堆叠的表面钝化质量和接触电阻率(ρc)尚未评估,将在未来的工作中解决。电学表征方面,利用玻璃替代结构提取霍尔参数(n, μ)以避免衬底导电,并利用四点探针测量硅片上的Rs。优化后的层用于传统n型TOPCon的后侧电子选择触点,光学损失较小;正面使用将需要额外的厚度最小化和光学重新优化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Results in Chemistry
Results in Chemistry Chemistry-Chemistry (all)
CiteScore
2.70
自引率
8.70%
发文量
380
审稿时长
56 days
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