Enhancing memory performance in IGZO-based 2T0C DRAM through comparative analysis of CAA and GAA FET structures

Abstract

As digital technology advances, the demand for high-performance, high-density, and low-power memory technologies continues to grow. To address these needs, the 2 Transistor 0 Capacitor (2T0C) DRAM architecture, featuring nondestructive read operations, has emerged as a promising alternative to conventional 1 Transistor 1 Capacitor DRAM. The InGaZnO (IGZO) channel material, known for low off-current and high mobility, enables long data retention and enhanced power efficiency in 2T0C DRAM. In this study, IGZO-based channel-all-around (CAA) and gate-all-around (GAA) FET structures were implemented using TCAD simulations, which were based on the well-calibrated physical carrier transport models with the measured IGZO channel device. The electrical characteristics, including the on/off-current ratio (I_on/I_off), were compared at the single-transistor level. For the 2T0C DRAM cell, variations in the gate length, critical dimension (CD), and underlap structure of the writing transistor (WTR) and reading transistor (RTR) were investigated, to evaluate memory characteristics such as data writing speed, retention, and single-cell disturbance, along with the feasibility of multi-bit operation. The analysis showed that the CAA structure provides faster data writing speeds, whereas the GAA structure—especially in the WTR configuration and 3 × 3 array design—offers significantly better retention and single-cell disturbance immunity. This study provides clear guidance for the structural optimization of IGZO-based 2T0C DRAM and practical insights into the designing next-generation high-density memory technologies.