Optimum design of a lateral superjunction considering charge imbalance due to process variations

Abstract

Lateral superjunctions (LSJ) are potential candidates for CMOS compatible high voltage devices in next-generation power integrated circuits. The prior works have modeled and developed design guidelines only for an ideal balanced LSJ, i.e., having equal charge in the n- and p-pillars. However, inevitable process variation during fabrication results in charge imbalance, \({k_{N}}\), that yields a breakdown voltage, \({V_\textrm{BR}}\), significantly lower than the target breakdown voltage, \({V_\textrm{BR,target}}\). In this work, we use the method of Lagrange multipliers to derive analytical equations for the optimum pillar parameters of an LSJ; these parameters yield the minimum specific ON-resistance, \({R_\textrm{ONSP}}\), for a \({V_\textrm{BR,target}}\) and \({k_{N}}\). The analytical solutions are verified using well-calibrated TCAD simulations for 0.1–1 kV Si LSJs and 1–10 kV 4H-SiC LSJs for \({k_{N}}\) from 0.05 to 0.30 (signifying 5 to 30% imbalance between the n- and p-pillar charge). Our solutions show that the optimum aspect ratio, \({r_{0}}\), varies between 8–12 for Si LSJs and 10–15 for 4H-SiC LSJs. Notably, our solution for an LSJ is found to yield significantly different optimum pillar parameters than our earlier solution for a vertical SJ for the same \({V_\textrm{BR}}\) and \({k_{N}}\), due to the difference in their dependency of \({R_\textrm{ONSP}}\) on the pillar parameters. This justifies the need for customized solution for the design of LSJ.