Tailoring Charge Trap Characteristics of Cobalt and Silicon Hybrid Nanostructure: Phases and Interface Effect of Thermal Treatment

Abstract

We systematically investigated the effect of post-deposition annealing temperature on the memory characteristics of a metal–oxide–insulator–oxide–semiconductor (MOIOS) structure utilizing cobalt–silicon hybrid nanostructures (CSHN) as the charge trapping layer (CTL). The MOIOS configurations were fabricated under identical conditions and thermally treated at five different temperatures from 530 to 880 °C. Capacitance–voltage (C–V) measurements revealed that only the structure annealed at 730 °C exhibited anti-clockwise hysteresis, a wide memory window width, and a flat-band voltage closest to 0 V, indicating ideal hole-only charge trapping behavior via the substrate. To elucidate the underlying mechanism, X-ray photoelectron spectroscopy (XPS) was employed to analyze the chemical states of cobalt and silicon atoms in the CTL. The results demonstrated that the optimal memory performance at 730 °C correlates with the formation of metallic cobalt nanostructures and the suppression of interfacial silicide bonding. Further analysis revealed that trap polarity is governed by the dominant cobalt oxide phase (CoO promotes hole trapping while Co₃O₄ favors electron trapping) and that interfacial bonding states influence the charge injection path. These findings provide a mechanistic interpretation linking thermal processing, chemical phase evolution, and charge transport behavior, thereby establishing a process–structure–property relationship critical for high-performance charge trap memory using CSHN-based materials.