Power-Law Reliability Plotting for Microelectronics.

Abstract

The power-law time plotting for reliability prediction needs to be reexamined. Until now, most degradation plots in microelectronics reliability analysis assume that the data follow a power-law change in time. The plot is the change in a measured parameter versus the log of time, based on the principle that one can calculate exactly the initial indicator value, S₀, and from that, extrapolate any change in that parameter, ΔS(t), as a power-law with time, t^1/m. The normalized change, ΔS(t)/S₀, relies heavily on a precise value for S₀ such that the calculated power-law exponent, m, may be exaggerated such that extrapolated time-to-fail calculations will be optimistic, even by many orders of magnitude. Also, the extrapolated lifetime may be pessimistic, also by orders of magnitude in time. We show that by transforming the x-axis as the time to a power of 1/m, choosing m by setting the second order of a polynomial curve fit to zero, a more accurate prediction can be achieved with a realistic time to fail given the accelerated testing conditions. We also show how to determine what the correct power of time is using a linear fit to a second-order polynomial. The plotting principles presented here are independent of any physics, rather an empirical focus on how to plot the data according to a power-law in time assumption.