Grain boundary-induced threshold voltage shift in dual-gate ZnO TFTs: an analytical and simulation approach

Abstract

An oxide-based dual-gate thin film transistor (DGTFT) is considered an attractive option for flat panel displays due to its exceptional optical transparency and electronic performance. In this study, we use ZnO as an oxide semiconductor material for the channel region having rectangular multiple grain boundaries (GBs) and HfO₂ as gate dielectric to analyze the effect of GBs on the performance of DGTFT. It is challenging to precisely determine the threshold voltage (V_th) in accumulation-mode TFTs due to trap states within the GBs in a disordered semiconductor. In the proposed work, when depleted these GBs are modeled as a continuous line of charge with a Gaussian trap distribution, resulting in an analytical expression correlating the V_th to the GB trap density. It shows that the V_th increases as GB trap density increases. Additionally, the effect of multiple GBs on the electrical properties of a double-gate ZnO TFT is examined using TCAD at various trap energy levels (E_mid) and trap change densities (N_t). The performance of DGTFT is analyzed in CMG (common-mode-gate) and GTG (grounded-top-gate) modes. It was observed that for 40 GBs with increasing trap concentration from 10¹⁰ to 10¹² cm⁻² eV⁻¹, the V_th value rises from 0.5 to 1.4 V in CMG Mode. In contrast, GTG mode increases the V_th value from 1.0 to 2.2 V.