Validation and verification of low power and area efficient fault model methods using 16nm technology

Abstract

With the advancement of Very Large-Scale Integration (VLSI), the integration of a high number of transistors on a single chip has significantly improved performance but also increased vulnerability to faults. To address this, we propose and validate fault-tolerant, low-power, and area-efficient circuit designs using 16nm CMOS technology. In this study, a comprehensive fault modeling approach is developed and demonstrated through two representative digital circuits-a full adder and a multiplexer. These circuits are used as case studies to evaluate the proposed fault models under both transient and permanent fault scenarios, including “stuck-at” fault conditions. Two self-repairing multiplexer architectures are introduced: one utilizing additional circuitry to correct faults, and another enabling internal gate-level self-repair. Both designs can detect and recover from single and multiple faults effectively. Furthermore, the full adder architecture incorporates error recovery mechanisms, enhancing system reliability. The proposed designs are simulated and validated using Tanner EDA at 16nm technology node, confirming their efficiency in terms of power, area, and fault tolerance.