{"title":"Low-power computing with reversible logic: a modular approach to Vedic multiplication","authors":"Diksha Ruhela, Rajni Jindal","doi":"10.1007/s10825-025-02396-1","DOIUrl":null,"url":null,"abstract":"<div><p>Driven by the growing imperative for energy-efficient computing, reversible logic gates have gained significant attention for their ability to reduce energy dissipation. These gates are essential in advanced domains such as quantum computing, DNA computing, nanotechnology, and energy-aware CMOS design. This study presents an optimized 4 × 4-bit complex Vedic multiplier designed using reversible logic, alongside modular implementations of a 4 × 4-bit Vedic multiplier, unified 8-bit adder–subtractor and two variants of a 4-bit carry-save adder. The proposed architectures are evaluated based on key performance metrics, including ancilla inputs, garbage outputs, quantum cost, and gate count. Furthermore, an entropy-based validation grounded in Shannon’s information theory confirms logical reversibility of the circuits, reinforcing their potential for ultra-low-power and quantum computing applications.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 5","pages":""},"PeriodicalIF":2.5000,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10825-025-02396-1","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Driven by the growing imperative for energy-efficient computing, reversible logic gates have gained significant attention for their ability to reduce energy dissipation. These gates are essential in advanced domains such as quantum computing, DNA computing, nanotechnology, and energy-aware CMOS design. This study presents an optimized 4 × 4-bit complex Vedic multiplier designed using reversible logic, alongside modular implementations of a 4 × 4-bit Vedic multiplier, unified 8-bit adder–subtractor and two variants of a 4-bit carry-save adder. The proposed architectures are evaluated based on key performance metrics, including ancilla inputs, garbage outputs, quantum cost, and gate count. Furthermore, an entropy-based validation grounded in Shannon’s information theory confirms logical reversibility of the circuits, reinforcing their potential for ultra-low-power and quantum computing applications.
期刊介绍：
he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered.
In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
