DS pOTFT 8T: Analysis of Dual data aware SRAM cell employing pentacene ditch formation on BGBC OTFT and LaxNb(1-x) Oy layer for high-speed, low-leakage flexible computing devices

Abstract

This work presents a novel Dual-Split Bottom Gate Bottom Contact (BGBC) 8T Static Random Access Memory (DS-pOTFT 8T SRAM) architecture featuring p+ doped pentacene ditched formation as the active channel material on LaxNb(1-x)Oy dielectric substrate. The innovative design addresses critical challenges in conventional silicon-based and organic thin-film transistor (OTFT) memory systems, including bitline (BL) leakage current, write-read conflicts, and subthreshold instability that increasingly plague System-on-Chip (SoCs) applications. Comprehensive Silvaco ATLAS simulations demonstrate exceptional performance improvements as 66% reduction in off-state leakage current compared to T6T designs and 39% versus DC8T architectures, while achieving 58% energy savings per bit operation. The dual data-aware word-line control mechanism enhances write static noise margin by 64%, increasing stability from 220 mV to 280 mV under low-voltage conditions. Read operations demonstrate 56\(\times\), 45\(\times\), 36\(\times\), and 28\(\times\) performance improvements over 6T, 7T, 8T, and 9T configurations respectively, while write operations show 32\(\times\), 41\(\times\), 15\(\times\), and 7\(\times\) enhancements. Power consumption analysis reveals substantial reductions by factors of 54\(\times\)-79\(\times\) during read operations and approximately 59x-82\(\times\) during write operations compared to baseline architectures. The strategic p+ doped ditch layer formation significantly improves charge carrier mobility while maintaining ultra-low leakage power of 0.6 nW. Write latency reduction of 22% and 40% improvement in read stability, combined with fastest write operation of about 19 pS, position this architecture as superior to existing Hybrid 6T pOTFT (H6T), Takamiya’s 6T (T6T), dual-threshold 8T CNTFET (DC8T), Fukuda 6T (F6T), data-scheme PMOS-NMOS 10T (DS10T), and BLE10T based SRAM designs. With only 12–15% area overhead, the DS-pOTFT 8T SRAM offers exceptional scalability for Computing-in-Memory (CIM) applications, flexible electronics and edge AI accelerators where energy efficiency and noise tolerance are paramount, representing a transformative advancement in next-generation memory architecture design.