Experimental study on a novel Si-Cu-based vapor chamber for chip heat dissipation

Abstract

The trend towards miniaturization and integration in integrated circuits has led to high power densities on chips. The thermal issues arising from higher heat flux not only limit the maximum operating frequency of chips but have also become a significant bottleneck hindering the performance of electronic chips. Integrating vapor chambers directly on the backside of semiconductor chips offers a promising solution by eliminating the need for thermal interface materials and effectively reducing package thermal resistance. However, challenges remain in enhancing heat flux during vapor chamber integration. To address this, three types of Si-Cu vapor chambers were designed and fabricated with wick structures made from Si and Cu materials. Capillary performance tests compared the capillary performance of bared silicon wafer and silicon micro-pillar wicks, revealing that processing micro-pillar wicks on the surface of silicon wafers significantly enhances capillary performance. Furthermore, an experimental system was constructed to test the heat transfer performance of various wick structure vapor chambers. Results showed that within a heating load range of 0 to 38 W, the surface temperature of the silicon wafer remained below 85℃, with a minimum thermal resistance for the vapor chamber at 0.436 K/W and a heat flux of 31.67 W/cm², indicating notable heat transfer performance for the silicon-copper vapor chamber. This study verified the feasibility of a silicon-copper composite vapor chamber, offering valuable insights for integration with flip-chip packaging and demonstrating significant application potential. This work serves as a reference for the integration and optimization of chip packaging.