Development of the front-end digital processing prototype chip for HFRS-TPC

IF 1.4 3区物理与天体物理 Q3 INSTRUMENTS & INSTRUMENTATION

Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment Pub Date : 2025-09-16 DOI:10.1016/j.nima.2025.171008

Weijian Lu , Yi Qian , Tianlei Pu , Songbo Chang , Hongyun Zhao , Zhikun Sun , Jiarui Zhang , Wankui Fu , Xiaofeng Fu

{"title":"Development of the front-end digital processing prototype chip for HFRS-TPC","authors":"Weijian Lu , Yi Qian , Tianlei Pu , Songbo Chang , Hongyun Zhao , Zhikun Sun , Jiarui Zhang , Wankui Fu , Xiaofeng Fu","doi":"10.1016/j.nima.2025.171008","DOIUrl":null,"url":null,"abstract":"<div><div>As the significant experimental facility of the High Intensity heavy ion Accelerator Facility (HIAF), the HIAF energy FRagment Separator (HFRS) will employ multiple Time Projection Chamber (TPC) detectors for particle identification and beam monitoring. This paper presents the architecture, design and test results of the Front-end Digital Processing (FDP) prototype chip for HFRS-TPC. The purpose is to reduce the amount of data and enhance transmission reliability, while improving integration and reducing power consumption. The chip is mainly composed of the top-level control module, channel data processing chains and serial output links. With configurable online data processing capabilities, the chip is designed to mitigate interference, minimize noise, compress data, reconstruct and optimize packets. Moreover, FDP supports trigger mode and trigger-less mode, with a single-channel count rate exceeding 180 kHz and a data transfer bandwidth of up to 250 Mbps. The FDP prototype chip has been fabricated in 180 nm CMOS process. Laboratory test results and further measurements joint with the TPC show that the chip functions in accordance with expectation and performs as designed.</div></div>","PeriodicalId":19359,"journal":{"name":"Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment","volume":"1082 ","pages":"Article 171008"},"PeriodicalIF":1.4000,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0168900225008101","RegionNum":3,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"INSTRUMENTS & INSTRUMENTATION","Score":null,"Total":0}

引用次数: 0

Abstract

As the significant experimental facility of the High Intensity heavy ion Accelerator Facility (HIAF), the HIAF energy FRagment Separator (HFRS) will employ multiple Time Projection Chamber (TPC) detectors for particle identification and beam monitoring. This paper presents the architecture, design and test results of the Front-end Digital Processing (FDP) prototype chip for HFRS-TPC. The purpose is to reduce the amount of data and enhance transmission reliability, while improving integration and reducing power consumption. The chip is mainly composed of the top-level control module, channel data processing chains and serial output links. With configurable online data processing capabilities, the chip is designed to mitigate interference, minimize noise, compress data, reconstruct and optimize packets. Moreover, FDP supports trigger mode and trigger-less mode, with a single-channel count rate exceeding 180 kHz and a data transfer bandwidth of up to 250 Mbps. The FDP prototype chip has been fabricated in 180 nm CMOS process. Laboratory test results and further measurements joint with the TPC show that the chip functions in accordance with expectation and performs as designed.

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HFRS-TPC前端数字处理原型芯片的研制

作为高强度重离子加速器（HIAF）的重要实验设备，高能碎片分离器（HFRS）将采用多个时间投影室（TPC）探测器进行粒子识别和束流监测。本文介绍了HFRS-TPC前端数字处理（FDP）原型芯片的结构、设计和测试结果。目的是减少数据量，提高传输可靠性，同时提高集成度，降低功耗。该芯片主要由顶层控制模块、通道数据处理链和串行输出链路组成。该芯片具有可配置的在线数据处理能力，旨在减轻干扰，最小化噪声，压缩数据，重构和优化数据包。FDP支持触发模式和无触发模式，单通道计数率超过180khz，数据传输带宽高达250mbps。FDP原型芯片采用180nm的CMOS工艺制作完成。实验室测试结果以及与TPC联合进行的进一步测量表明，该芯片的功能符合预期，性能符合设计要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment 物理-光谱学

CiteScore

3.20

自引率

21.40%

发文量

787

审稿时长

1 months

期刊介绍： Section A of Nuclear Instruments and Methods in Physics Research publishes papers on design, manufacturing and performance of scientific instruments with an emphasis on large scale facilities. This includes the development of particle accelerators, ion sources, beam transport systems and target arrangements as well as the use of secondary phenomena such as synchrotron radiation and free electron lasers. It also includes all types of instrumentation for the detection and spectrometry of radiations from high energy processes and nuclear decays, as well as instrumentation for experiments at nuclear reactors. Specialized electronics for nuclear and other types of spectrometry as well as computerization of measurements and control systems in this area also find their place in the A section. Theoretical as well as experimental papers are accepted.