Area-Efficient Cascode Inductive Source-Degenerated CMOS LNA for GPS L1 Band

Abstract

In this paper, an area-efficient low-noise amplifier for GPS L1 band application is designed. Besides the requirements of noise figure (NF), bandwidth, and input matching, the design methodology has been focused on the area efficiency. As a design example, a prototype L1 band LNA is implemented using standard 0.11 μm CMOS technology. The design is based on a conventional cascode inductive source-degenerated topology, but special care has been dedicated to the three inductors. To reduce cost, specifically by minimizing on-chip area and imposing constraints on power consumption, the source inductor is implemented using a bond wire. As the dominant contributor of silicon area, the drain inductor has been optimized in a very area-efficient way. The design trade-off between input matching and noise matching is consequently adopted to achieve minimized NF. Measurement results indicate that the LNA achieves a measured power gain of 14.3 dB at 1.57 GHz with a NF of 1.37 dB, while consuming 1.9 mA from a standard 1.8 V supply and occupying a chip area of 300 × 230 μm.