FINFET Based IL 7 T SRAM Cell: Reliable, Silicon Area- and Power Efficient for Use in Portable Medical Equipment

Abstract

Portable biomedical devices aim to serve in human life at a reasonable cost. The portable devices having significant impact due to compact size and durable battery operation. The pixel information is storing in embedded memory for biomedical image processing equipment, where the pixel values hold vital information about the image. Static random-access memory (SRAM) is used in the majority of embedded memories for storing this vital information. To holds vital data, SRAM needs to be extremely reliable, stable and low in power consumption. The proposed research presents a revolutionary low-energy, silicon area efficient, robust FinFET based Intramural loop 7 T (IL 7 T) SRAM bit cell that achieves a large read static margin while operating in weak inversion region (lowering the supply voltage to lower power dissipation). It provides numerous of benefits in terms of area, power, latency over few current existing designs. In contrast to the traditional MOSFET based TG8T, 9 Transistors SRAM architectures, the proposed cell offers decrease in latency (Read delay / Access Time-τ_ra) of 42.8%, 57.4%, a significant rise in ‘static voltage noise margin’ (SVNM) of 42.1% and 81.1%, and a limiting leakage power dissipation of 84.5% and 33.19%. Including the lower energy consumption and high reliability, the proposed work occupies in small silicon area. The 7 transistors are used in one memory cell, it requires 1.02X less area overhead than a conventional MOSFET based 6 T memory cell. This cell has the greatest performance metrics out of all the SRAM cells under consideration for compression. The used design functioned under weak inversion region and obtained the optimum performance metrics in memory design at a 300 mV supply voltage for biomedical applications.