An Optimized Hetero-gate Bandgap-Engineered SOI PNPN TFET with Hetero-dielectric BOX for Near-Complete Suppression of Ambipolar Current

Abstract

This paper presents a planar SOI Tunnel FET that integrates a source-side pocket, hetero-gate, hetero-dielectric BOX along with bandgap engineering. These design enhancements, implemented through 2D simulations, result in a significantly high ON current, an improved ON-to-OFF current ratio, and nearly complete suppression of ambipolar current. An optimum pocket is introduced near the source leading to full depletion of the pocket. A comprehensive analysis of partial depletion and full depletion conditions along with a detailed step by step flow for fabrication of the proposed device is presented. As part of bandgap engineering, SiGe is utilized as the source material. Additionally, the hetero-gate structure enhances the tunneling generation rate between the source and the channel, achieving an ON-current of 2 × 10^–4 A/µm and an OFF current of 3.37 × 10^–15 A/µm. The incorporation of a hetero-dielectric buried oxide (HDB) effectively suppresses ambipolar conduction up to a gate voltage of -1.1V. These design optimizations collectively yield a better ON-to-OFF current ratio of 6 × 10¹⁰ and nearly eliminate OFF current. Furthermore, the device achieves a point subthreshold swing of approximately 20 mV/dec, making it a strong candidate for low-power and energy-efficient applications.