Electrolyte-gated junctionless III-V Nanowire transistors: a TCAD-based evaluation

Abstract

In this study, we explore the operation and performance of electrolyte-gated junctionless III-V nanowire (NW) transistors featuring compositionally graded In_xGa_1-xAs channels. These devices leverage the electric double-layer (EDL) gating mechanism at the electrolyte/semiconductor interface to achieve ultra-high charge carrier densities, surpassing those possible with conventional oxide dielectrics. Fermi–Dirac statistics are introduced by a numerical method to reproduce associated charge densities of EDL transistors. A 1 nm interfacial HfO₂ layer is introduced to capture the electrostatics of the EDL, prevent charge transfer between the electrolyte and the semiconductor, and mimic the Stern layer. Device simulations are conducted to optimize the heterostructured NW composition and doping profile, followed by benchmarking against traditional HfO₂-gated structures. The EDL-gated device achieves an I_ON/I_OFF ratio of 10⁶, with a subthreshold slope of 60 mV/dec and a threshold voltage of 0.31 V at a low drain voltage of 0.3 V, indicating a two-order magnitude improvement over conventional junctionless oxide-gated NW transistors. Computational methodologies include finite element modeling in COMSOL to extract voltage-dependent ion densities and subsequent device simulations using Silvaco's Atlas software. The results indicate that the optimized EDL-gated device exhibits superior electrostatic integrity and performance metrics compared to conventional gating methods. The findings underscore the potential of EDL gating in III-V NW configurations for advanced electronic applications, demonstrating significant improvements in switching characteristics and power efficiency. Further optimization and exploration of bias-dependent ionic concentrations and configurable device geometries highlight the robustness and scalability of this approach for next-generation low-power electronics.